An embodiment of the present invention relates to the field of integrated circuit design, and, more particularly, to an approach for datapath layout.
Due to aggressive density and performance goals of many integrated circuit datapath designs, conventional computer aided design (CAD) automation tools that are not designed with datapath layout requirements in mind may produce unacceptable datapath layout results. High-performance datapath layout is, therefore, often performed manually. Using this approach, layout design of datapaths may consume a large portion of layout resources for some current integrated circuit design projects. For a typical high-performance microprocessor, for example, required layout resources may be on the order of hundreds of layout designer years with the result that datapath circuit and layout design is often the critical path of a corresponding project timeline.
The layout effort needed for a particular project is roughly proportional to the number of drawn devices in the integrated circuit design. As integrated circuit design size grows exponentially (per Moore's law), the manpower needed for manual datapath design will soon become prohibitively expensive and time-consuming and therefore, impractical.